Due to advancement of semiconductor technology, memory has increasingly great capacity and increasingly high speed. At present, NOR flash memory is widely used in electronic products. NOR memory comprises a plurality of banks each having a plurality of blocks. The blocks each comprise a plurality of cells arranged in columns and rows. In general, the cells of each block share a P well and a N well. According to the prior art, to erase cells of a row in a block, it is necessary to apply an erasing voltage (which is usually a relatively high positive voltage, such as 8V) to the P well and apply a negative voltage (which is usually a relatively high negative voltage, such as −9V) to the gate of the cells of the row, so as to erase data from cells. However, a system power voltage or a positive voltage (usually a relatively low positive voltage, such as VCC or 3V) lower than the erasing voltage has to be applied to the gate of the “not-to-be-erased” cells of the remaining rows in the same block, thereby resulting in erase disturb during an erasure process.
In general, small blocks are relatively insusceptible to erase disturb. However, chip dimensions increases with the quantity of blocks. As a result, application of NOR flash memory is currently restricted to one-time erasure of 4K bits (i.e., a sector) or 64K bits (i.e., a block). The prior art is not effective in eliminating erase disturb. According to the prior art, to reduce erase disturb that occurs to a memory having a specific number of rows, it is necessary to divide the memory into more blocks or sectors. To divide the memory into more blocks or sectors, it requires more power switching decoding circuits and a driving circuit in order to generate a voltage signal; however, in doing so, chip dimensions increase.
Referring to FIG. 1 and FIG. 2, there are shown in FIG. 1 a schematic view of conventional arrangement of banks of a flash memory, and in FIG. 2 a circuit block diagram of a driving circuit of a conventional NOR flash memory, referring to area A of FIG. 1. A conventional NOR flash memory has a plurality of driving circuits. The driving circuit 10 is disposed between two neighboring blocks (such as BLOCK_n) of two neighboring banks (such as BANK_0, BANK_1). The driving circuit 10 comprises a word line driving circuit WL_DRIVER, two block P well voltage supplying circuits BGPW1, BGPW2, 16 negative voltage supplying circuits VNNI_X16, and a bit line driving circuit YDSL_DRIVER. In general, each sector has 4K bits (i.e., each sector has 4K cells), and each block (such as BLOCK_0, BLOCK_1) has 16 sectors (i.e., each block has 64K cells.) In general, the word line driving circuit WL_DRIVER has a plurality of word line preceding drivers WL_pre_Driver. The word line preceding drivers WL_pre_Driver drive 16 left word lines LWL_X16 and 16 right word lines RWL_X16 in order to drive the cells of two neighboring blocks (such as BLOCK_n), respectively.
The two block P well voltage supplying circuits BGPW1, BGPW2 receive a system power Y_POWER for supplying a positive voltage to the P well and the N well of the two neighboring blocks BLOCK_n. The word line driving circuit WL_DRIVER receives 16 power sources X_POWER_X16 from a power switching decoding circuit (not shown) and generates and sends 16 word line driving signals to the gate of a plurality of cells of a plurality of rows. The bit line driving circuit YDSL_DRIVER receives the system power Y_POWER and drives a plurality of bit lines YBL of the two neighboring blocks BLOCK_n. The 16 negative voltage supplying circuits VNNI_X16 each receive a negative voltage VNNG, and then the 16 negative voltage supplying circuits VNNI_X16 generate and send 16 negative voltages to the word line driving circuit WL_DRIVER in accordance with the negative voltage VNNG, to erase a selected word line of 16 sectors of the two blocks BLOCK_n.
To erase a plurality of cells of a row of a sector, the word line driving circuit WL_DRIVER applies a negative voltage to a word line of the row, wherein the word line of the row is connected to the gate of a plurality of cells of the row. In the block to which the cells to be erased belong, a system power voltage is applied to a plurality of word lines of the cells not to be erased. If the block does not have any cells to be erased, a ground voltage (0V) supplied by the word line driving circuit WL_DRIVER will be applied to all the word lines of the block.
As regards a conventional NOR flash memory, the driving circuit 10 is disposed in the space between two neighboring blocks in two neighboring banks, respectively, and the space that accommodates the driving circuit 10 is an elongate space which separates BLOCK_0 and BLOCK_1 and separates BLOCK_2 and BLOCK_3 shown in FIG. 1, respectively. Therefore, to reduce erase disturb, the NOR flash memory must have more blocks or sectors. A plethora of inhibitive voltage circuits and excessive partition of sectors complicate the word line driving circuit. To further expand blocks or banks, it is necessary to allocate a driving circuit of a conventional NOR flash memory repeatedly at the cost of increasing the area occupied.